Raster I is an innovative hardware renderer designed for real-time rasterization, harnessing the power of a Tile-Based Deferred Rendering (TBDR) architecture. With a specialized focus on efficiency and performance, Raster I integrates several advanced graphics features, making it a cutting-edge solution for graphics processing. Key implementations include hardware-accelerated transform and lighting (T&L), deferred Phong shading, double buffering, VSync, MSAA anti-aliasing, ordered dithering, and back-face culling.

Key Features:

• Tiled Rasterization: Employs a Pineda-style rasterizer that breaks the screen into tiles, allowing for efficient memory access and enhanced rendering performance.
• Multi-Cycle Vertex Transformer: Capable of processing complex vertex transformations to deliver high-quality graphics output.
• Deferred Shading: Uses a deferred shading pipeline that calculates lighting effects for each pixel based on interpolated data, optimizing rendering time.

Raster I supports output resolutions up to 1024x768 at 60Hz, rendering tiles of size 64x32 sequentially. It achieves high graphical fidelity with features like ordered dithering for pseudo 24bpp pixels and MSAA 4x anti-aliasing while ensuring minimal computational overhead.

Performance Metrics:

• Utilizes 69% LUT, 97% BRAM, and 88% DSP resources on the Digilent Arty A7-100T FPGA.
• Capable of rendering complex 3D models with up to 3,000 faces at 30 frames per second.
• Operates on a clock frequency of 100MHz, providing a robust platform for high-performance graphics.

Architecture Overview:

The architecture is organized into three clock domains: system, graphics, and display, all functioning at 100MHz, while the display operates at 65MHz. This division enhances performance by allowing parallel processing of graphics and display tasks.

The rendering unit follows a three-stage data flow: vertex transformation, pixel interpolation, and deferred shading. This structure streamlines the graphics pipeline, ensures effective memory usage, and reduces the time required for rendering complex scenes.

Display Unit:

The display unit synchronizes with the VGA output, managing frame updates during the horizontal and vertical blanking intervals. It leverages techniques like ordered dithering for color approximation and gamma correction to optimize color accuracy in rendering.

Future Development:

As the initial iteration of Project Raster, Raster I signifies the foundation for future enhancements. Upcoming versions aim to introduce features like GPGPU ISA, further expanding its capabilities and solidifying its position as a comprehensive open-source hardware solution for modern graphics applications.