SeqiLog (pronounced seh-kwi-log) is an innovative Python library designed for logic design and verification, tailored specifically for developers engaging with hardware simulation at the register transfer level (RTL).

Key Features

SeqiLog offers an array of powerful features that make hardware design intuitive and efficient:

• Hierarchical, Parameterized Module Design: Create complex hardware systems using a modular architecture that promotes reusability and organization.
• Four-State bits Data Structure: Utilize a multidimensional array data type that supports comprehensive logic design, enhancing simulation capabilities.
• Asynchronous Discrete Event Simulation: Leverage Python's async / await syntax to perform discrete event simulations seamlessly.

Declarative and Strict

SeqiLog embraces a declarative approach, allowing designers to focus on defining what components to use rather than how they interact with the task scheduling algorithm. Its strict nature ensures that functions will raise exceptions for inconsistent argument types, promoting robust design practices. Uninitialized or metastable states propagate pessimistically, providing a fail-safe mechanism during simulation.

Pythonic Meta-HDL API

Experience a pioneering Pythonic meta-Hardware Description Language (HDL), currently a work in progress, which aims to redefine how hardware designers interact with software development principles. Users should be prepared for potential breaking changes as the library evolves.

Example Usage

To illustrate the capabilities of SeqiLog, consider the following implementation of a D flip flop (DFF) with the D input connected to the inverted Q output:

from vcd import VCDWriter
from seqlogic import Module, Vec, run, sleep

async def drv_clock(y):
    """Positive clock w/ no phase shift, period T=2, 50% duty cycle."""
    while True:
        y.next = "1b1"
        await sleep(1)
        y.next = "1b0"
        await sleep(1)

async def drv_reset(y):
    """Positive reset asserting from T=[1..2]"""
    y.next = "1b0"
    await sleep(1)
    y.next = "1b1"
    await sleep(1)
    y.next = "1b0"

class Top(Module):
    """Data flip flop (DFF) Example"""

    def build(self):
        clk = self.logic(name="clk", dtype=Vec[1])
        rst = self.logic(name="rst", dtype=Vec[1])
        q = self.logic(name="q", dtype=Vec[1])
        d = self.logic(name="d", dtype=Vec[1])

        self.expr(d, ~q)
        self.dff_r(q, d, clk, rst, rval="1b0")
        self.drv(drv_clock(clk))
        self.drv(drv_reset(rst))

# Run simulation w/ VCD dump enabled
with (
    open("dff.vcd", "w") as f,
    VCDWriter(f, timescale="1ns") as vcdw,
):
    top = Top(name="top")
    top.dump_vcd(vcdw, ".*")
    run(top.elab(), ticks=20)

Utilize tools like GTKWave or Surfer to visualize the VCD wave dumps created during simulations. This example demonstrates the ease and effectiveness of modeling digital logic circuits using SeqiLog.

Explore additional examples within the ipynb and tests directories to gain deeper insights into the library's functionalities.

SeqiLog is available on PyPI and supports Python versions 3.12 and above, making it a versatile tool for contemporary hardware design challenges.